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Low cost fault-tolerant routing algorithm for Networks-on-Chip

Liu, Junxiu, Harkin, Jim, Li, Yuhua and Maguire, Liam 2015. Low cost fault-tolerant routing algorithm for Networks-on-Chip. Microprocessors and Microsystems 39 (6) , pp. 358-372. 10.1016/j.micpro.2015.06.002

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Abstract

A novel adaptive routing algorithm – Efficient Dynamic Adaptive Routing (EDAR) is proposed to provide a fault-tolerant capability for Networks-on-Chip (NoC) via an efficient routing path selection mechanism. It is based on a weighted path selection strategy, which exploits the status of real-time NoC traffic made available via monitor modules. The key performance goal is to maintain throughput under congested and faulty conditions via effective routing path decisions. In the proposed EDAR, port weights are calculated in real-time according to the channel status – Idle/Busy/Congested/Faulty, and the port with the lowest weighting is ranked as the near-optimal route to forward packets. This mechanism enables the router to bypass congested ports and tolerate faulty ports. To assess the latency and throughput of the proposed routing algorithm, several traffic patterns for both fault-free and faulty NoCs were evaluated. Results show that EDAR can achieve higher throughput compared to other state of the art routing algorithms under various traffic patterns and levels of injected faults. In addition, the hardware area overhead for EDAR is demonstrated to have a reasonably low cost which maintains scalability for large NoC implementations.

Item Type: Article
Date Type: Publication
Status: Published
Schools: Computer Science & Informatics
ISSN: 0141-9331
Last Modified: 20 Feb 2020 14:30
URI: http://orca.cf.ac.uk/id/eprint/129145

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